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Beginner's Corner / Re: here are some practicing sources
« on: December 27, 2015, 02:22:14 pm »
thanks!, +1
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General discussion / Re: What were your Christmas presents?
« on: December 26, 2015, 01:34:53 pm »
perfume
wallet
amazon kindle
wallet
amazon kindle
3
Hardware / Re: Recommendations for Android Phones.
« on: December 26, 2015, 01:29:58 pm »
i've a OnePlus One and is great!
i quote considering nexus as well
i quote considering nexus as well
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Anonymity and Privacy / Re: autistici vpn connection problems
« on: December 26, 2015, 01:24:07 pm »5
Beginner's Corner / Re: Discover all IP addresses in a Local network.
« on: December 26, 2015, 01:00:22 pm »
arpscan?
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Hardware / Re: noob Q
« on: June 08, 2015, 12:05:59 am »yeah, ok thanks for the reply. You look pretty advanced in your understanding of machine behavior, i am also curious about
why one uses C for manipulating memory & pointers, why use such low level programming when one can just depend on the compiler?
I think that the more you have to manage low level things, the more you have to use low level languages, up to the verilog...
-------------------
| Ln | <-- Application
-------------------
| . | <-- OS
-------------------
| . | <-- Assembler
------------------
| L1 | <-- Firmware
-------------------
every level has languages that fits best for the pourpose, and in each level languages have different vision of the system.... in firmware programming you have vision of all registers and modules, in assembly level you can view less register but you have more "power" (you can call procedures!), in c you don't see any register(see register keyword) but you can manage pointers (and have sockets!), in (Objective)$LANGUAGE(++|#|*) you can have generic programming, regexp, ecc.
you must write the scheduler for your OS, or the memory manager for your OS, what language you think you'll use? :)
I found these in pdf section, maybe other noob will find them useful:this is usefull too:
http://upload.evilzone.org/download.php?id=9242941&type=zip
http://evilzone.org/ebooks/inside-the-machine-an-illustrated-introduction-to-microprocessors-and-computer/
btw your English looks pretty solid
"What Every Programmer Should Know About Memory" --> https://people.freebsd.org/~lstewart/articles/cpumemory.pdf
As always, sorry for my english ( i'll write this on my signature asap :)
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Hardware / Re: noob Q
« on: June 03, 2015, 04:05:07 pm »
i'll try to explain you:
every processor has a little banch of general purpose registers and a smaller banch of private registers,
the number of registers is implementation dependent and, just for example, private registers include 1 register for the current istruction e 1 for program counter.
every processor makes the loop:
- fetch
- decode
- execute
- check interruption
now, we assume 1 single processor not parallel, and this code ( i use D-RISC for this example)
in our example we have 7 istruction and a for loop that will be executed N times:
so we have (1 (CLEAR) + 6 * N (LOOP)) * T
were T is the average time that processor does the work of fetch, decode, execute, check interrupt.
every time processor wants to fetch an istruction send a request to a module (MMU) that does the translation from logical address to fisical address.
MMU speaks with L1 cache and returns the istruction to processor (if there is not a fault, at this point i will talk about paginated memory, segmented memory, TLBs, ecc., too long...).
processor --> MMU --> TLB --> L1 --> ...
for every fetch (and eventualy, other access to the memory for istruction m-m or r-m).
when processor owns the istruction ( in IR register) can do the decodification and the execution of the istruction.
every istruction (class of istruction) has different T (Register-Register arithmetical short operation can have 1 clock circle to execute,ecc).
if there are cache faults we have (1 + 6*N) * Tex + Nfault * Tfault
I have written enough, for pipeline processors or multicore or istruction cache e data cache you have to understand this before.
this are the concepts i have, probably is only didattic stuff, but is the best i can do.
if someone has less didattic, more real world experience/concepts correct me.
as always, sorry for my english
every processor has a little banch of general purpose registers and a smaller banch of private registers,
the number of registers is implementation dependent and, just for example, private registers include 1 register for the current istruction e 1 for program counter.
every processor makes the loop:
- fetch
- decode
- execute
- check interruption
now, we assume 1 single processor not parallel, and this code ( i use D-RISC for this example)
Code: [Select]
CLEAR R2
loop: LOAD R1, R2, R3
LOAD R4, R2, R5
ADD R3, R5, R6
STORE R7, R2, R6
INCR R2
IF< R2, R8, loop
this can be Code: [Select]
for (i = 0; i < N; i++) C[i] = A[i] + B[i];in our example we have 7 istruction and a for loop that will be executed N times:
so we have (1 (CLEAR) + 6 * N (LOOP)) * T
were T is the average time that processor does the work of fetch, decode, execute, check interrupt.
every time processor wants to fetch an istruction send a request to a module (MMU) that does the translation from logical address to fisical address.
MMU speaks with L1 cache and returns the istruction to processor (if there is not a fault, at this point i will talk about paginated memory, segmented memory, TLBs, ecc., too long...).
processor --> MMU --> TLB --> L1 --> ...
for every fetch (and eventualy, other access to the memory for istruction m-m or r-m).
when processor owns the istruction ( in IR register) can do the decodification and the execution of the istruction.
every istruction (class of istruction) has different T (Register-Register arithmetical short operation can have 1 clock circle to execute,ecc).
if there are cache faults we have (1 + 6*N) * Tex + Nfault * Tfault
I have written enough, for pipeline processors or multicore or istruction cache e data cache you have to understand this before.
this are the concepts i have, probably is only didattic stuff, but is the best i can do.
if someone has less didattic, more real world experience/concepts correct me.
as always, sorry for my english
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